A 5.4GHZ WIDE TUNING RANGE CMOS PLL USING AN AUTO-CALIBRATION MULTIPLE-PASS RING OSCILLATOR

被引：0
|
作者：
Lu, Ping [1 ]
Chen, Danfeng [1 ]
Ye, Fan [1 ]
Ren, Junyan [1 ]
机构：
[1] Fudan Univ, ASIC & Systme State Key Lab, Shanhai, Peoples R China
来源：
IEEE INTERNATIONAL SOC CONFERENCE, PROCEEDINGS | 2009年
关键词：
D O I：
暂无
中图分类号：
TM [电工技术]; TN [电子技术、通信技术];
学科分类号：
0808 ; 0809 ;
摘要：
A 5.4GHz multiple-pass ring voltage controlled oscillator (VCO) based phase-locked loop (PLL) is described. For the sake of active devices' sensitivity to process and temperature regarding ring oscillators, an effective automatic frequency calibration scheme is proposed. A new process-independent differential to single (DTOS) is used to adjust control voltage range and loop gain. The chip is implemented in 0.18-urn CMOS process and achieves phase noise of -100dBc/Hz@1MHz and a 40% tuning range.
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页码：39 / 42
页数：4
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