A sub-word parallel digital signal processor for wireless communication systems

被引：0
|
作者：
Huang, YH [1 ]
Chiueh, TD [1 ]
机构：
[1] Natl Taiwan Univ, Dept Elect Engn, Taipei 10617, Taiwan
来源：
2002 IEEE ASIA-PACIFIC CONFERENCE ON ASIC PROCEEDINGS | 2002年
关键词：
digital signal processor; subword parallel MAC; FFT butterfly;
D O I：
暂无
中图分类号：
TP3 [计算技术、计算机技术];
学科分类号：
0812 ;
摘要：
In this paper, we propose a programmable fixed-point digital signal processor for wireless communications. The architecture of the processor is designed according to the computation requirements of modern communication systems. A decimation-in-frequency (DIF) butterfly unit is built in the processor to enhance the processing capability of FFT operations needed in orthogonal-frequency-division-multiplexing (OFDM) systems. In addition, the butterfly unit can be reconfigured to accelerate squared-difference and add-compare-select calculation in the Viterbi algorithms. A new sub-word parallel complex-valued multiply-and-accumulate (MAC) architecture is proposed to execute complex/real and single/ double precision operations, making it suitable for different requirements of signal formats in signal processing for communication transceivers.
引用
收藏
页码：287 / 290
页数：4
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