Exploiting high-performance DSP hardware for real-time CELP implementation

被引：0
|
作者：
Teo, TT [1 ]
Tan, EC [1 ]
Premkumar, AB [1 ]
机构：
[1] Nanyang Technol Univ, Sch Appl Sci Comp Engn, Singapore 639798, Singapore
来源：
IEEE TENCON'97 - IEEE REGIONAL 10 ANNUAL CONFERENCE, PROCEEDINGS, VOLS 1 AND 2: SPEECH AND IMAGE TECHNOLOGIES FOR COMPUTING AND TELECOMMUNICATIONS | 1997年
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D O I：
暂无
中图分类号：
TP18 [人工智能理论];
学科分类号：
081104 ; 0812 ; 0835 ; 1405 ;
摘要：
We describe our experience of implementing a CELP algorithm on a TMS320C44 digital signal processing board. The particular implementation we consider is the Federal Standard 1016 (FS1016) 4.8 Kbps CELP vocoder. Our main focus here is on exploiting the highperformance architecture and features of the DSP processor for possible real-time applications.
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收藏
页码：421 / 424
页数：4
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