A Polyphase Nonlinear Equalization Architecture and Semi-blind Identification Method

In this paper, we present an architecture and semi-blind identification method for a polyphase nonlinear equalizer (pNLEQ). Such an equalizer is useful for extending the dynamic range of time-interleaved analog-to-digital converters (ADCs). Our proposed architecture is a polyphase extension to other architectures that partition the Volterra kernel into small nonlinear filters with relatively low computational complexity. Our semi-blind identification technique addresses important practical concerns in the equalizer identification process. We describe our architecture and demonstrate its performance with measured results when applied to a National Semiconductor ADC081000.