System level voltage scheduling technique using UML-RT model

被引：0
|
作者：
Neishaburi, M. H. [1 ]
Daneshtalab, Masoud [1 ]
Nabi, Majid [1 ]
Mohammadi, Simak [1 ]
机构：
[1] Univ Tehran, Tehran, Iran
来源：
2007 IEEE/ACS INTERNATIONAL CONFERENCE ON COMPUTER SYSTEMS AND APPLICATIONS, VOLS 1 AND 2 | 2007年
关键词：
D O I：
10.1109/AICCSA.2007.370928
中图分类号：
TP31 [计算机软件];
学科分类号：
081202 ; 0835 ;
摘要：
In this paper, we present optimized methodology for Intra-task voltage scheduling. Our proposed method gets data flow and control flow of application that represents coloration between different parts of the application at the early stage of design using UML.-RT model and decides to schedule processor's voltage. By applying this technique on JPEG encoder system experimental results show reduction in energy consumption by 18-54 % over common Intra-DVS algorithm.
引用
收藏
页码：500 / +
页数：3
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