Exploiting FPGA-based architectures and design tools for problems of reconfigurable computations

This paper addresses the design and implementation,a of a configurable "combinatorial processor", a computational device, which call be used for solving different combinatorial problems. These call be characterized by a set of variables having a limited number of values with a corresponding set of operations that might be applied to these variables. Different mathematical models call be used to describe such tasks. We adopted a matrix representation, which is easier to treat in digital devices. The operations on discrete matrices art unique and cannot be efficiently performed on a general-purpose processor Although the number of such operations grows exponentially with the number of variables, to solve a particular combinatorial problem a very small number of such operations is usually required. Hence the importance of providing for dynamic change of operations. The paper presents an approach allowing the run-time modification of combinatorial computations via reloading the RAM-based configurable logic blocks of the FPGAs.