An efficient design-for-testability scheme for 2-D transform in H.264 advanced video coders

In this paper, an easily design-for-testability (DfT) scheme based on C-testability conditions is adopted to implement test syntheses of the 2-D forward, inverse and Hadamard transforms suggested in H.264 advanced video coders (AVC). The proposed testable scheme is applied to bit-level regular arrangement for the transform architecture. It guarantees 100% fault coverage while the resulting number of test pattern is only 8. The proposed integrated transforms have been synthesized with UMC 0.18 mu m technology. Under the small performance degradation, simulation results show that the DfT implementation increases about only 12% area overhead compared with the original circuit.