Low-voltage pipelined ADC using class-AB pseudo-differential OTA

被引：0
|
作者：
Chaloenlarp, W [1 ]
Thanachayanont, A [1 ]
机构：
[1] King Mongkuts Inst Technol Ladkrabang, Fac Engn, Dept Elect Engn, Microelect Res Lab,Res Ctr Commun & Informat Tech, Bangkok 10520, Thailand
来源：
IEEE INTERNATIONAL SYMPOSIUM ON COMMUNICATIONS AND INFORMATION TECHNOLOGIES 2004 (ISCIT 2004), PROCEEDINGS, VOLS 1 AND 2: SMART INFO-MEDIA SYSTEMS | 2004年
关键词：
D O I：
暂无
中图分类号：
TP18 [人工智能理论];
学科分类号：
081104 ; 0812 ; 0835 ; 1405 ;
摘要：
This paper describes the design of a low-voltage low-power pipelined analog-to-digital converter using a new class-AB pseudo-differential operational transconductance amplifier (OTA). The class-AB OTA employed in this work makes use of partial positive feedback to enhance its transconductance, which allows large gain-bandwidth product with low power dissipation. A 6-bit 15.36-MS/s pipelined ADC has been designed using a 0.35-mu m CMOS process. Simulation results show that the ADC can achieve a maximum DNL and INL of 0.5 LSB and 0.59 LSB, respectively, and an SFDR of 47.5 dB, while draining 2.8 mA from a 2 V supply voltage.
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页码：128 / 132
页数：5
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