Validation of an advanced encryption standard (AES) IP core

被引：0

作者：

Tomashau, V ^{[1
]}

Kean, T ^{[1
]}

机构：

[1] Algotronix Ltd, Edinburgh EH8 8YD, Midlothian, Scotland

来源：

12TH ANNUAL IEEE SYMPOSIUM ON FIELD-PROGRAMMABLE CUSTOM COMPUTING MACHINES, PROCEEDINGS | 2004年

关键词：

D O I：

10.1109/FCCM.2004.61

中图分类号：

TP3 [计算技术、计算机技术];

学科分类号：

0812 ;

摘要：

This paper describes the package of test bench code required to verify the Algotronix' AES IP Core. Several authors (see the references in [3]) have published papers detailing the implementation of the Advanced Encryption Standard (AES) on FPGA chips; however, the design goals of this AES core are somewhat different from previous work. Rather than emphasizing performance OUT design emphasizes portability and customer confidence in the security of the VHDL code.

引用

页码：291 / 292

页数：2

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