Quad-Band Receiver for GSM/GPRS/EDGE in 90nm digital CMOS

被引：0
|
作者：
Duelger, Fikret [1 ]
Fang, Sher Jiun [1 ]
Mohieldin, Ahmed Nader [1 ]
Fontaine, Paul [1 ]
Bellaouar, Abdellatif [1 ]
Frechette, Michel [1 ]
机构：
[1] Texas Instruments Inc, Wireless Terminals Business Unit, RF Design Grp, Dallas, TX 75243 USA
来源：
2006 IEEE INTERNATIONAL SYMPOSIUM ON CIRCUITS AND SYSTEMS, VOLS 1-11, PROCEEDINGS | 2006年
关键词：
RF CMOS; LNA; mixer; GSM; GPRS; EDGE; ADC; receiver; noise figure; noise figure under blocking condition; IIP3; LO leakage;
D O I：
暂无
中图分类号：
TP3 [计算技术、计算机技术];
学科分类号：
0812 ;
摘要：
A Quad-Band GSM/GPRS/EDGE receiver front-end including I and Q ADCs designed in 90nm Digital CMOS technology is presented. The low band receiver designed for GSM850/GSM900 achieves 33dB gain, 1.9dB noise figure, 7.5dB of noise figure under blocking condition and -20dBm of in-band HP3 with a power of 68mW, while the high band DCS/PCS receiver achieves 32dB gain, 2.2dB noise figure, 9.3dB of noise figure under blocking condition and -20dBm of in-band IIP3 with a power of 72mW. Total active area occupies 3 mm(2).
引用
收藏
页码：3057 / +
页数：2
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