MODELING AND SIMULATION OF A NANOSTRUCTURE FOR A SINGLE ELECTRON TECHNOLOGY IMPLEMENTATION

The Electronic Devices Simulators are valuable tools used in micro and nano-electronics labs. This paper analyses the electrical characteristics evolution, under the down-scaling sizes tendency of the SOI devices. A nanostructure sub-10nm Si film thickness with a vacuum cavity in the device body was simulated. The global current is a superposition of a tunnel current through the cavity and an inversion current at the film bottom. The tunnel source-drain current prevails in devices with sub 10nm film thickness and provides the I-D-V-DS characteristics with a minimum. For film thickness comprised between 200-10nm, the I-D-V-GS curves preserve similar shapes with a classical MOS/SOI's transfer characteristics. For sub 10nm film thickness, the shape of the I-D-V-GS characteristics tends to have a maximum, like in Single Electron Device SED.