A partitioned wavelet-based approach for image compression using FPGA's

Discrete wavelet transformations (DWT) followed by embedded zerotree encoding is a very efficient technique (EZT) for image compression [1, 2, 3]. However, the algorithms proposed in literature assume random access to the whole image. This makes the algorithms unsuitable for hardware solutions because of extensive access to external memory. Here, we introduce efficient FPGA hardware approaches for DWT for lossless and lossy image compression targeting the minimization of external memory accesses. In particular, the approaches allow both parallel wavelet transformation and parallel embedded zero tree encoding.