Automatic layout of scalable embedded field programmable gate array

被引：1

作者：

Mrabet, H ^{[1
]}

Marrakchi, Z ^{[1
]}

Mehrez, H ^{[1
]}

Tissot, A ^{[1
]}

机构：

[1] Univ Paris 06, ASIM Lab, LIP6, F-75252 Paris, France

来源：

ICEEC'04: 2004 INTERNATIONAL CONFERENCE ON ELECTRICAL, ELECTRONIC AND COMPUTER ENGINEERING, PROCEEDINGS | 2004年

关键词：

D O I：

10.1109/ICEEC.2004.1374502

中图分类号：

TP18 [人工智能理论];

学科分类号：

081104 ; 0812 ; 0835 ; 1405 ;

摘要：

This paper presents a layout technique for scalable embedded Field Programmable Gate Array architecture (eFPGA). It describes the total flow to generate a variety of eFPGA architectures using parameterized generators and Alliance CAD developed in the university of Paris6. We will show one example of realization using a symbolic library of cells. Our test eFPGA have a symmetric mesh architecture (Island-style) composed of five main tiles. The scalability of this tiles can be varied to obtain the best design fit on the System on Chip device.

引用

页码：469 / 472

页数：4

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