Optimization of Receiver FIFO for IEEE 802.3ba 40GBASF, PCS Sub Layer

被引：0

作者：

Nanayakkara, Anuradha ^{[1
]}

Thayaparan, Subramaniam ^{[1
]}

机构：

[1] Univ Moratuwa, Dept Elect & Telecommun Engn, Moratuwa, Sri Lanka

来源：

2016 INTERNATIONAL CONFERENCE ON INFORMATION NETWORKING (ICOIN) | 2016年

关键词：

IEEE802.3ba; Receiver FIFO; lane alignment; clock rate compensation; 64B/66B;

D O I：

暂无

中图分类号：

TP [自动化技术、计算机技术];

学科分类号：

0812 ;

摘要：

This paper analyses the receiver of 40GBASE PCS Sub layer specified by IEEE 802.3ba CSMA/CD standards. Based on the analysis, possible optimization parameters for the receiver FIFO are identified. Proper functionality of the proposed design is verified with simulation results. The optimization of receiver FIFO design may lead to reduce the gate count, area and power consumption in ASIC design.

引用

页码：151 / 154

页数：4