Performance analysis of Banyan switch architecture

The advancement in the field of computer technology, communication and the increasing user demand in terms of bandwidth and speed, the future communication network is rolling towards the BISDN with optical technology. The high speed ATM network is one of the major tool used for BISDN. In turn, the efficiency of the ATM network relies on the switching fabric. Hence, the switching fabric of future telecommunication systems should have a very low cell loss and delay performance. In this paper, the simulation results of Sort Banyan architecture of size 8 x 8 are presented. The simulation of Sort Banyan network is performed along with four different, methods in view of enhancing the throughput of the Sort Banyan switch network. The cell loss and delay performance versus the cell arrival rate for the four schemes viz, Input buffer, Interstage buffer, Shared output buffer and Regeneration of cells using FEC method are presented for both Poisson and Self-similar traffic models.