A methodology for dependability evaluation of the time-triggered architecture using software implemented fault injection

Fault injection has become a valuable methodology for dependability evaluation of computer systems. Software implemented fault injection is used because of the relative simplicity of injecting faults. In this paper we present a methodology for assessment of the error detection mechanisms of the Time-Triggered Architecture (TTA) bus structure by emulating hardware faults using software implemented fault injection. The TTA is an architecture for distributed embedded safety-critical real-time applications which have high dependability requirements. At the core of the architecture is the time-triggered communication protocol TTP/C running on a dedicated communication controller. In the TTA fail-silence is a main concern, thus high error detection coverage with small error detection latency is required. Temporal intrusiveness of the software fault injector is measured and analyzed. A fault injection tool set for use in experimental assessment of newer chip implementations of the TTPC communication controller, is developed.