XPRESS: A cell layout generator with integrated transistor folding

被引：10
|
作者：
Gupta, A [1 ]
The, SC [1 ]
Hayes, JP [1 ]
机构：
[1] INTEL CORP,DESOGM TECHNOL DIV,SANTA CLARA,CA 95052
来源：
EUROPEAN DESIGN & TEST CONFERENCE 1996 - ED&TC 96, PROCEEDINGS | 1996年
关键词：
D O I：
10.1109/EDTC.1996.494331
中图分类号：
TP3 [计算技术、计算机技术];
学科分类号：
0812 ;
摘要：
引用
收藏
页码：393 / 400
页数：8
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