A Jitter Measurement Circuit Based On Dual Resolution Vernier Oscillator

被引：1
|
作者：
Tang, Wei [1 ]
Feng, Jianhua [1 ]
Lee, Chunglen [2 ]
机构：
[1] Peking Univ, Key Lab Integrated Microsyst Shenzhen, Dept Microelect, Beijing, Peoples R China
[2] Natl Chiao Tung Univ, Coll Elect & Comp Engn, Hsinchu 30050, Taiwan
来源：
2009 IEEE 8TH INTERNATIONAL CONFERENCE ON ASIC, VOLS 1 AND 2, PROCEEDINGS | 2009年
基金：
中国国家自然科学基金;
关键词：
timing jitter; on-chip; vernier oscillator; jitter measurement;
D O I：
10.1109/ASICON.2009.5351194
中图分类号：
TM [电工技术]; TN [电子技术、通信技术];
学科分类号：
0808 ; 0809 ;
摘要：
This paper presents a new on-chip jitter measurement circuit based on a dual vernier oscillator (VO) structure. The new structure measures the jitter with a low resolution VO first and then with a high resolution VO, thus greatly expanding the measurement range of the jitter and reducing the test time. The oscillators are implemented with differential digital controlled delay elements, whose oscillation periods can be precisely controlled The circuit has been implemented and verified with the SMIC 0.18 mu m technology and has been shown to have the ability of measuring jitters in the pico-second range.
引用
收藏
页码：1213 / +
页数：2
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