Development of high-stability, low-leakage 6Tr-SRAM with single data line and single power supply using SOTB process

This paper proposes a single data line, double-word line 6Tr-SRAM for use in Internet of Things (IoT) devices using a silicon-on-thin-BOX (SOTB) process to achieve a high reliability and a low power consumption. The layout area was reduced compared to a conventional 6Tr structure by using a uniform data line. The proposed SRAM is able to generate multiple electric potentials without the need for additional power sources by employing a self-controllable voltage level (SVL) circuit, which is a simplified form of a DC/DC converter. Further, it expands the operating margin for writes and reads by decreasing the memory cell supply voltage and increasing the memory-cell supply ground voltage in writes, and by dropping the word line potential when reading. When the variance of the threshold (V-t) was 0 (TT) and the power supply voltage (V-DD) was 1.2 V, the read and write margins expanded by multiples of 2.09 and 1.31 of the conventional 6Tr SRAM, respectively. The standby power caused by a leakage when data is being saved under the same conditions was reduced to 9.17% of that of the conventional SRAM. The area overhead the SVL circuit was 1.383% of that of the conventional form.