Asymmetric Sizing in a 45nm 5T SRAM to Improve Read Stability over 6T

被引：19

作者：

Nalam, Satyanand ^{[1
]}

Calhoun, Benton H. ^{[1
]}

机构：

[1] Univ Virginia, Dept Elect & Comp Engn, Charlottesville, VA 22903 USA

来源：

PROCEEDINGS OF THE IEEE 2009 CUSTOM INTEGRATED CIRCUITS CONFERENCE | 2009年

关键词：

D O I：

10.1109/CICC.2009.5280733

中图分类号：

TM [电工技术]; TN [电子技术、通信技术];

学科分类号：

0808 ; 0809 ;

摘要：

This paper describes a 5-transistor (5T) SRAM bitcell that uses a novel asymmetric sizing approach to achieve increased read stability. Measurements of a 32 kb 5T SRAM in a 45nm bulk CMOS technology validate the design, showing read functionality below 0.5V. The 5T bitcell has lower write margin than the 6T, but measurements of the 45nm 5T array confirm that a write assist method restores comparable writability with a 6T down to 0.7 V.

引用

页码：709 / 712

页数：4

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