Reconfigurable system for high-speed and diversified AES using FPGA

被引：22
|
作者：
Jing, Ming-Haw
Chen, Zih-Heng
Chen, Jian-Hong
Chen, Yan-Haw
机构：
[1] I Shou Univ, Dept Informat Engn, Sect 1, Ta Hsu Hsiang 840, Kaohsiung Cty, Taiwan
[2] Fortune Inst Technol, Dept Comp Sci & Informat Engn, Lyouciyou Village 831, Kaohsiung Cty, Taiwan
来源：
MICROPROCESSORS AND MICROSYSTEMS | 2007年 / 31卷 / 02期
关键词：
advanced encryption standard (AES); diversity; field programmable gate arrays (FPGAs); reconfigurable system; Rijndael;
D O I：
10.1016/j.micpro.2006.02.018
中图分类号：
TP3 [计算技术、计算机技术];
学科分类号：
0812 ;
摘要：
In this article, we present a FPGA-based reconfigurable system for the advanced encryption standard (AES) algorithm. This proposed design, called diversified AES (DAES), has the variations of four parameters: the field irreducible polynomial, the affine transformation in the SubBytes, the offsets in the ShiftRows, and the polynomial in the MixColumms. The advantage of such variations in the AES system is that they increase the strength regarding internal or external attacks. We also use straightforward architecture - took-up tables for encryption and decryption to lead this system simple and high-speed using field programmable gate arrays (FPGAs). (c) 2006 Elsevier B.V. All rights reserved.
引用
收藏
页码：94 / 102
页数：9
相关论文
共 50 条
  • [1] Accelerating FCM Algorithm Using High-Speed FPGA Reconfigurable Computing Architecture
    Almomany, Abedalmuhdi
    Jarrah, Amin
    Al Assaf, Anwar
    [J]. JOURNAL OF ELECTRICAL ENGINEERING & TECHNOLOGY, 2023, 18 (04) : 3209 - 3217
  • [2] Accelerating FCM Algorithm Using High-Speed FPGA Reconfigurable Computing Architecture
    Abedalmuhdi Almomany
    Amin Jarrah
    Anwar Al Assaf
    [J]. Journal of Electrical Engineering & Technology, 2023, 18 : 3209 - 3217
  • [3] An improved method about AES and FPGA high-speed realize
    Ren Wenping
    Zhang Wenyong
    He Jiqin
    Shen Dongya
    [J]. 2016 IEEE INTERNATIONAL CONFERENCE OF ONLINE ANALYSIS AND COMPUTING SCIENCE (ICOACS), 2016, : 334 - 337
  • [4] Fault resistant encryption system using high speed AES algorithm on FPGA
    Chorage, S. S.
    Somwanshi, V. A.
    [J]. 2017 INTERNATIONAL CONFERENCE OF ELECTRONICS, COMMUNICATION AND AEROSPACE TECHNOLOGY (ICECA), VOL 2, 2017, : 466 - 470
  • [5] Design of High Speed AES System for Efficient Data Encryption and Decryption System using FPGA
    Kumar, Santhosh R.
    Shashidhar, R.
    Mahalingaswamy, A. M.
    Kumar, Praveen M. S.
    Roopa, M.
    [J]. 2018 3RD INTERNATIONAL CONFERENCE ON ELECTRICAL, ELECTRONICS, COMMUNICATION, COMPUTER, AND OPTIMIZATION TECHNIQUES (ICEECCOT - 2018), 2018, : 1279 - 1282
  • [6] FPGA-based reconfigurable system for tool condition monitoring in high-speed machining process
    Sevilla-Camacho, P. Y.
    Robles-Ocampo, J. B.
    Jauregui-Correa, J. C.
    Jimenez-Villalobos, D.
    [J]. MEASUREMENT, 2015, 64 : 81 - 88
  • [7] Reconfigurable architecture for high-speed implementations of DES, 3DES and AES
    Gao, Na-Na
    Li, Zhan-Cai
    Wang, Qin
    [J]. Tien Tzu Hsueh Pao/Acta Electronica Sinica, 2006, 34 (08): : 1386 - 1390
  • [8] AES Encryption and Decryption Algorithm for High-Speed Design FPGA-Based
    Zhou Yong-hong
    Shao Jin-xiang
    Xiao Shun-wen
    Tang Zheng-ming
    [J]. NATIONAL CONFERENCE OF HIGHER VOCATIONAL AND TECHNICAL EDUCATION ON COMPUTER INFORMATION, 2010, : 266 - +
  • [9] Implementation of high-speed high-resolution data conversion system using FPGA
    Cao Xiaoqiu
    Zeng Jin
    Yang Tao
    [J]. ICEMI 2007: PROCEEDINGS OF 2007 8TH INTERNATIONAL CONFERENCE ON ELECTRONIC MEASUREMENT & INSTRUMENTS, VOL IV, 2007, : 862 - 864
  • [10] Design of a High-speed Reconfigurable Serial Fieldbus with Reliable Communication Based on FPGA
    Zhao Xuejin
    Liu Zhuqing
    Hu Tianliang
    Zhang Chengrui
    [J]. MECHATRONICS AND INTELLIGENT MATERIALS II, PTS 1-6, 2012, 490-495 : 2125 - 2130
12345