39% access time improvement, 11% energy reduction, 32 kbit 1-read/1-write 2-port static random-access memory using two-stage read boost and write-boost after read sensing scheme

被引：0

作者：

Yamamoto, Yasue ^{[1
]}

Moriwaki, Shinichi ^{[2
]}

Kawasumi, Atsushi ^{[3
]}

Miyano, Shinji ^{[4
]}

Shinohara, Hirofumi ^{[5
]}

机构：

[1] Socionext Inc, Kyoto 6018414, Japan

[2] Socionext Inc, Yokohama, Kanagawa 2220033, Japan

[3] Toshiba Co Ltd, Kawasaki, Kanagawa 2128520, Japan

[4] STARC, Yokohama, Kanagawa 2220033, Japan

[5] Waseda Univ, Kitakyushu, Fukuoka 8080135, Japan

来源：

JAPANESE JOURNAL OF APPLIED PHYSICS | 2016年 / 55卷 / 04期

关键词：

SRAM;

D O I：

10.7567/JJAP.55.04EF13

中图分类号：

O59 [应用物理学];

学科分类号：

摘要：

We propose novel circuit techniques for 1 clock (1CLK) 1 read/1 write (1R/1W) 2-port static random-access memories (SRAMs) to improve read access time (tAC) and write margins at low voltages. Two-stage read boost (TSR-BST) and write word line boost (WWL-BST) after the read sensing schemes have been proposed. TSR-BST reduces the worst read bit line (RBL) delay by 61% and RBL amplitude by 10% at V-DD = 0.5 V, which improves tAC by 39% and reduces energy dissipation by 11% at V-DD = 0.55 V. WWL-BST after read sensing scheme improves minimum operating voltage (V-min) by 140 mV. A 32 kbit 1CLK 1R/1W 2-port SRAM with TSR-BST and WWL-BST has been developed using a 40 nm CMOS. (C) 2016 The Japan Society of Applied Physics

引用

页数：6