Design of a High-Speed Block Interleaving/Deinterleaving Architecture for Wireless Communication Applications

被引：5

作者：

Yu, Chu ^{[1
]}

Yen, Mao-Hsu ^{[2
]}

Hsiung, Pao-Ann ^{[3
]}

Chen, Sao-Jie ^{[4
]}

机构：

[1] Natl ILan Univ, Dept Elect Engn, Yilan 260, Taiwan

[2] Natl Taiwan Ocean Univ, Dept Comp Sci & Engn, Keelung, Taiwan

[3] Natl Chung Cheng Univ, Dept Comp Sci & Informat Engn, Chiayi, Taiwan

[4] Natl Taiwan Univ, Grad Inst Elect Engn, Taipei, Taiwan

来源：

2009 IEEE INTERNATIONAL CONFERENCE ON CONSUMER ELECTRONICS | 2009年

关键词：

D O I：

10.1109/ISCAS.2009.5117729

中图分类号：

TM [电工技术]; TN [电子技术、通信技术];

学科分类号：

0808 ; 0809 ;

摘要：

This paper presents a high-speed block interleaver/deinterleaver designed to prevent burst errors in wireless communications. Using FIFO banks, our proposed architecture is a high-speed design that owns lower hardware complexity and consumes lower power dissipation. Especially, the simple finite-state-machine control unit used in our design can provide an arbitrary column-wise permutation for the block interleaver.

引用

页码：237 / +

页数：2

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