Power Efficient SAR ADC Designed in 90 nm CMOS Technology

被引：0

作者：

Singh, Vijay Pratap ^{[1
]}

Sharma, Gaurav Kumar ^{[1
]}

Shukla, Aasheesh ^{[1
]}

机构：

[1] GLA Univ, IET, Dept ECE, Mathura, India

来源：

2017 2ND INTERNATIONAL CONFERENCE ON TELECOMMUNICATION AND NETWORKS (TEL-NET) | 2017年

关键词：

SAR; DAC; ADC; Comparator; Power dissipation; ARCHITECTURE;

D O I：

暂无

中图分类号：

TM [电工技术]; TN [电子技术、通信技术];

学科分类号：

0808 ; 0809 ;

摘要：

A 8-bit Successive Approximation Register (SAR) Analog to Digital Converter (ADC) is designed using non redundant SAR structure and sequencer/code Register structure for low power operation. The designed ADC structures provide optimum results for all three circuit design challenges: speed, area and power. Among the two designed SAR ADCs, non redundant SAR structure ADC and sequence/code register SAR structure ADC is power efficient than SAR ADC designed for the same feature size. Design and simulation of various SAR ADCs has been done in 90 nm CMOS Technology.

引用

页码：286 / 290

页数：5

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