TS-LDPC codes: Turbo-structured codes with large girth

被引：8
|
作者：
Lu, Jin [1 ]
Moura, Jose M. F.
机构：
[1] Sun Microsyst, Louisville, CO 80028 USA
[2] Carnegie Mellon Univ, Dept Elect & Comp Engn, Pittsburgh, PA 15213 USA
来源：
IEEE TRANSACTIONS ON INFORMATION THEORY | 2007年 / 53卷 / 03期
基金：
美国安德鲁·梅隆基金会;
关键词：
error floor; girth; interleaver; low-density parity-check (LDPC) codes; turbo-structured;
D O I：
10.1109/TIT.2006.890690
中图分类号：
TP [自动化技术、计算机技术];
学科分类号：
0812 ;
摘要：
We consider turbo-structured low-density parity-check (TS-LDPC) codes-structured regular codes whose Tanner graph is composed of two trees connected by an interleaver. TS-LDPC codes with good girth properties are easy to construct: careful design of the interleaver component prevents short cycles of any desired length in its Tanner graph. We present algorithms to construct TS-LDPC codes with arbitrary column weight j >= 2 and row weight k and arbitrary girth g. We develop a linear complexity encoding algorithm for a type of TS-LDPC codes-encoding friendly TS-LDPC (EFTS-LDPC) codes. Simulation results demonstrate that the bit-error rate (BER) performance at low signal-to-noise ratio (SNR) is competitive with the error performance of random LDPC codes of the same size, with better error floor properties at high SNR.
引用
收藏
页码：1080 / 1094
页数：15
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