All-Optical Half-Adder Using All-Optical XOR and AND Gates for Optical Generation of oSumo and oCarryo

In this article, a numerical simulation study using the symmetric planar three-core non-linear directional coupler, operating with a short light pulse (2 ps), for the implementation of an all-optical half-adder is presented. The half-adder is the key building block for many digital processing functions such as shift register, binary counter, and serial parallel data converters. Optical couplers are an important component for application in optical fiber telecommunication systems and all integrated optical circuits because of very high switching speeds (as high as the femto-second range). In this numerical simulation, the symmetric planar three-core non-linear directional coupler presents a planar symmetrical structure with three cores in a parallel equidistant arrangement, three logical inputs (CP, A, and B), and two output logic functions (C and S). The CP(phi) input is a control pulse with a phase difference phi = (0 2) between inputs A and B (logical inputs of the half-adder) and one amplitude discriminator circuit. The half-adder uses two output logic functions of Sum(S) and Carry(C), which can be demonstrated by using XOR and AND gates, respectively. For the half-adder, the phase [phi MIN, phi MAX] intervals are studied, allowing the operation of the device as a half-adder. For the selected range of CP(phi BETTER), the extinction ratio was studied, the compression factors for both Sum(S) and Carry(C) outputs of the symmetric planar three-core non-linear directional coupler.