A 40nm 256kb 6T SRAM with Threshold Power-Gating, Low-Swing Global Read Bit-Line, and Charge-Sharing Write with Vtrip-Tracking and Negative Source-Line Write-Assists

This paper presents a 256kb 6T static random access memory (SRAM) with threshold power-gating (TPG), low-swing global read bit-line (GRBL), and charge-sharing write with Vtrip (VTP) tracking and negative source-line (NVSL) write-assists (WA). The TPG facilitates lower NAP mode voltage/power and faster wake-up for the cell array, while low-swing GRBL reduces the dynamic read power. A variation-tolerant charge-sharing write scheme, where the floating "Low" global write bit-line (GWBL) is used to capacitively couple down the local bit-line (LBL), is combined with a cell Vtrip-tracking and NVSL write-assists to improve the write-ability. The 256kb test chip is implemented in UMC 40nm low-power (LP) CMOS technology. Error-free full-functionality is achieved from 1.18GHz at 1.5V to 100MHz at 0.65V without redundancy. The TPG scheme reduces the power by 70% (55%) at 1.5V (0.5V) in NAP mode. The low-swing GRBL reduces dynamic read power by 3.5% (8%) at 1.1V (0.65V). The VTP-WA and NVSL-WA improve the write V-MIN by 50mV (from 0.7V to 0.65V) and reduce write bit failure rate by 2.75x at 0.65V.