Analog and RF circuits in 45 nm CMOS and below: planar bulk versus FinFET

被引：0

作者：

Wambacq, Piet ^{[2
]}

Verbruggen, Bob ^{[2
]}

Scheir, Karen ^{[2
]}

Borremans, Jonathan ^{[2
]}

De Heyn, Vincent ^{[1
]}

Van der Plas, Geert ^{[1
]}

Mercha, Abdelkarim ^{[1
]}

Parvais, Bertrand ^{[1
]}

Subramanian, Vaidy ^{[3
]}

Jurczak, Malgorzata ^{[1
]}

Decoutere, Stefaan ^{[1
]}

Dormay, Stephane ^{[1
]}

机构：

[1] IMEC, Kapeldreef 75, B-3001 Louvain, Belgium

[2] Vrije Univ Brussel, Brussels, Belgium

[3] Katholieke Univ Leuven, Leuven, Belgium

来源：

ESSCIRC 2006: PROCEEDINGS OF THE 32ND EUROPEAN SOLID-STATE CIRCUITS CONFERENCE | 2006年

关键词：

D O I：

暂无

中图分类号：

TP3 [计算技术、计算机技术];

学科分类号：

0812 ;

摘要：

Scaling to 45 nm node and below might necessitate the use of new processing steps (e.g. new gate stacks) or new device concepts such as FinFETs. Although intrinsic transistor speed increases with scaling, some analog performance parameters tend to degrade. In this paper we show with experimental results and simulations on analog and RF circuits that for high-speed and RF applications, downscaling to 45 nm channel length of bulk devices still improves RF circuit performance, while for low-frequency, high-gain applications FinFET technology offers better circuit performance than planar bulk CMOS.

引用

页码：54 / +

页数：2

共 50 条

[1] Analog and RF circuits in 45 nm CMOS and below: planar bulk versus FinFET
Wambacq, Piet
Verbruggen, Bob
Scheir, Karen
Borremans, Jonathan
De Heyn, Vincent
Van der Plas, Geert
Mercha, Abdelkarim
Parvais, Bertrand
Subramanian, Vaidy
Jurczak, Malgorzata
Decoutere, Stefaan
Donnay, Stephane
[J]. ESSDERC 2006: PROCEEDINGS OF THE 36TH EUROPEAN SOLID-STATE DEVICE RESEARCH CONFERENCE, 2006, : 53 - 56
[2] SOI FinFET versus Bulk FinFET for 10nm and below
Hook, Terence B.
Allibert, F.
Balakrishnan, K.
Doris, Bruce
Guo, Dechao
Mavilla, Narasimha
Nowak, E.
Tsutsui, G.
Southwick, R.
Strane, J.
Sun, Xin
[J]. 2014 IEEE SOI-3D-Subthreshold Microelectronics Technology Unified Conference (S3S), 2014,
[3] Design of UWB LNA in 45nm CMOS technology: Planar bulk vs. FinFET
Ponton, D.
Palestri, P.
Esseni, D.
Selmi, L.
Tiebout, M.
Parvais, B.
Knoblinger, G.
[J]. PROCEEDINGS OF 2008 IEEE INTERNATIONAL SYMPOSIUM ON CIRCUITS AND SYSTEMS, VOLS 1-10, 2008, : 2701 - +
[4] FinFET technology for analog and RF circuits
Parvais, B.
Subramanian, V.
Mercha, A.
Dehan, M.
Wambacq, P.
Sanssen, W.
Groeseneken, G.
Decoutere, S.
[J]. 2007 14TH IEEE INTERNATIONAL CONFERENCE ON ELECTRONICS, CIRCUITS AND SYSTEMS, VOLS 1-4, 2007, : 182 - +
[5] Planar bulk MOSFETs versus FinFETs: An analog/RF perspective
Subramanian, Vaidy
Parvais, Bertrand
Borremans, Jonathan
Mercha, Abdelkarim
Linten, Dirnitri
Wambacq, Piet
Loo, Josine
Dehan, Morin
Gustin, Cedric
Collaert, Nadine
Kubicek, Stefan
Lander, Robert
Hooker, Jacob
Cubaynes, Florence
Donnay, Stephane
Jurczak, Malgorzata
Groeseneken, Guido
Sansen, Willy
Decoutere, Stefaan
[J]. IEEE TRANSACTIONS ON ELECTRON DEVICES, 2006, 53 (12) : 3071 - 3079
[6] Perspective of RF design in future planar and FinFET CMOS
Borremans, J.
Parvais, B.
Dehan, M.
Thijs, S.
Wambacq, P.
Mercha, A.
Kuijk, M.
Carchon, G.
Decoutere, S.
[J]. 2008 IEEE RADIO FREQUENCY INTEGRATED CIRCUITS SYMPOSIUM, VOLS 1 AND 2, 2008, : 63 - +
[7] Evaluation of 10-nm Bulk FinFET RF Performance-Conventional Versus NC-FinFET
Singh, R.
Aditya, K.
Parihar, S. S.
Chauhan, Y. S.
Vega, R.
Hook, T. B.
Dixit, A.
[J]. IEEE ELECTRON DEVICE LETTERS, 2018, 39 (08) : 1246 - 1249
[8] Design Challenges and Techniques for 5nm FinFET CMOS Analog/Mixed-Signal Circuits
Goyal, Saurabh
Wadhwa, Sanjay Kumar
Tripathi, Divya
Agrawal, Gaurav
Thakur, Krishna
Jain, Deependra Kumar
Loke, Alvin L. S.
Kumar, Atul
Upadhyay, Manish Kumar
Bhawna
Dey, Sanjoy Kumar
[J]. 2023 36TH INTERNATIONAL CONFERENCE ON VLSI DESIGN AND 2023 22ND INTERNATIONAL CONFERENCE ON EMBEDDED SYSTEMS, VLSID, 2023, : 98 - 103
[9] Scaling CMOS beyond Si FinFET: an analog/RF perspective
Parvais, B.
Hellings, G.
Simicic, M.
Weckx, P.
Mitard, J.
Jang, D.
Deshpande, V
van Liempc, B.
Veloso, A.
Vandooren, A.
Waldron, N.
Wambacq, P.
Collaert, N.
Verkest, D.
[J]. 2018 48TH EUROPEAN SOLID-STATE DEVICE RESEARCH CONFERENCE (ESSDERC), 2018, : 158 - 161
[10] 14-nm FinFET Technology for Analog and RF Applications
Singh, Jagar
Ciavatti, J.
Sundaram, K.
Wong, J. S.
Bandyopadhyay, A.
Zhang, X.
Li, S.
Bellaouar, A.
Watts, J.
Lee, J. G.
Samavedam, S. B.
[J]. IEEE TRANSACTIONS ON ELECTRON DEVICES, 2018, 65 (01) : 31 - 37

← 1 2 3 4 5 →