A Single-Chip 4K 60-fps 4:2:2 HEVC Video Encoder LSI Employing Efficient Motion Estimation and Mode Decision Framework With Scalability to 8K

被引:14
|
作者
Onishi, Thkayuki [1 ]
Sano, Takashi [1 ]
Nishida, Yuldkuni [1 ]
Yokohari, Kazuya [1 ]
Nakamura, Ken [1 ]
Nitta, Koyo [2 ]
Kawashima, Kimiko [3 ]
Okamoto, Jun [3 ]
Ono, Naoki [1 ]
Sagata, Atsushi [1 ]
Iwasaki, Hiroe [1 ]
Ikeda, Mitsuo [1 ]
Shimizu, Atsushi [1 ]
机构
[1] NTT Corp, NTT Media Intelligence Labs, Yokosuka, Kanagawa 2390847, Japan
[2] NTT Device Innovat Ctr, Atsugi, Kanagawa 2430198, Japan
[3] NTT Corp, NTT Network Technol Labs, Tokyo 1808585, Japan
关键词
Digital video broadcasting; high-efficiency video coding (HEVC); motion estimation (ME); multichip configuration; video codecs;
D O I
10.1109/TVLSI.2018.2842179
中图分类号
TP3 [计算技术、计算机技术];
学科分类号
0812 ;
摘要
A professional-image-quality video encoder LSI for broadcasting and content distribution has been developed with single-chip 4K 60-fps 4:2:2 high-efficiency video coding (HEVC) encoding capability and 8K ultrahigh definition television scalability. Edge-based intramode pruning and statistically adaptive multiblock-size motion estimation (ME) efficiently reduce HEVC's high computational complexity for real-time processing, while a deeply centralized-mode decision framework maintains high compression performance. Internal reference image caches with 797-Gb/s image feed capability support the 768-GOPS ME computation of distributed motion vector search. Interchip pictures and data exchange features with high-speed data buses are also used for multichip 8K encoding configuration. A subjective evaluation showed that the proposed encoder LSI maintained the same visual quality as an encoder LSI complying with the previous standard while reducing bit rate by 40%. The chip was designed and fabricated in a 28-nm CMOS technology and used to build industry-leading 4K and 8K broadcasting systems.
引用
收藏
页码:1930 / 1938
页数:9
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