Implementation of an Interleaved ZVS Forward Converter

被引：0
|
作者：
Lin, B. R. [1 ]
Chiang, H. K. [1 ]
Chen, J. J. [1 ]
Cheng, J. -J [1 ]
Cheng, C. Y. [1 ]
机构：
[1] Natl Yunlin Univ Sci & Technol, Dept Elect Engn, Yunlin 640, Taiwan
来源：
2009 INTERNATIONAL CONFERENCE ON POWER ELECTRONICS AND DRIVE SYSTEMS, VOLS 1 AND 2 | 2009年
关键词：
DESIGN; MODE;
D O I：
暂无
中图分类号：
TM [电工技术]; TN [电子技术、通信技术];
学科分类号：
0808 ; 0809 ;
摘要：
A parallel zero voltage switching (ZVS) forward converter with half-bridge topology is presented in this paper. Two converter modules are connected in parallel in the output side to share the load current. In the primary side, two converter modules use the same power switches so that the semiconductor devices are reduced in the proposed converter compared with the conventional interleaved half-bridge converter. The asymmetrical pulse-width modulation (APWM) is used to regulate the output voltage and realize the ZVS turn-on of switches at the transition interval. The voltage stress of switches is clamped at the input source voltage. The system analysis, operation principle and design consideration of the proposed converter are presented. Finally experimental results based on a laboratory prototype are provided to verify the effectiveness of the proposed converter.
引用
收藏
页码：128 / 133
页数：6
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