Integrated end-to-end delay analysis for regulated ATM networks

In this paper, we present an efficient and effective method to derive the worst case end-to-end delay analysis. By utilizing the inverse of these arrival and service functions, we can effectively compute the worst case delay of an ATM switch. We analyze and compare the performance of an ATM switch with priority driven and FIFO scheduling policies using different workload sets and under different utilization. We also compare the performance using our proposed "integrated" method always produced a better estimation of cell delay within an ATM network.