FPGA-based Acceleration of Word2vec Using OpenCL

被引：4

作者：

Ono, Taisuke ^{[1
]}

Shoji, Tomoki ^{[1
]}

Waidyasooriya, Hasitha Muthumala ^{[1
]}

Hariyama, Masanori ^{[1
]}

Aoki, Yuichiro ^{[2
]}

Kondoh, Yuki ^{[2
]}

Nakagawa, Yaoko ^{[2
]}

机构：

[1] Tohoku Univ, Grad Sch Informat Sci, Aoba Ku, 6-3-09 Aramaki Aza Aoba, Sendai, Miyagi 9808579, Japan

[2] Hitachi Ltd, Res & Dev Grp, Kokubunji, Tokyo 1858601, Japan

来源：

2019 IEEE INTERNATIONAL SYMPOSIUM ON CIRCUITS AND SYSTEMS (ISCAS) | 2019年

关键词：

Word embedding; FPGA; machine learning; natural language processing;

D O I：

10.1109/iscas.2019.8702700

中图分类号：

TM [电工技术]; TN [电子技术、通信技术];

学科分类号：

0808 ; 0809 ;

摘要：

Word2vee is a word embedding method that converts words into vectors in such a way that the semantically and syntactically relevant words are close to each other in the vector space. The processing time of Word2vec is very large due to the huge data size. We propose a power efficient FPGA-based accelerator designed using OpenCL. We achieved 13.4 times speed-up compared to single-core CPU implementation with only 53W of power consumption. The proposed FPGA-based accelerator has the highest power-efficiency compared to existing top-end GPU-based accelerators.

引用

页数：5

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