Temperature-Dependent Test Scheduling with TAM Bus Wire Assignment Considered for Core-Based SoC Designs

Recent researches have shown that temperature-dependent testing, which applies different tests at different temperature ranges, is needed for core-based system-on-chip SoC designs. However, previous temperature-dependent test scheduling approaches assume that two tests cannot utilize the test-access mechanism TAM at the same time. In fact, if the tests of different cores do not use the same TAM bus wire, they can be executed concurrently for reducing the test application time. Based on this observation, in this paper, we propose two-phase algorithm to perform temperature-dependent test scheduling with TAM bus wire assignment considered for core-based SoC designs. Compared with previous approaches, experimental data consistently show that the proposed approach can greatly reduce the total test application time.