MOTIM - A scalable architecture for Ethernet switches

The main goal of this work is to describe a scalable and reusable architecture useful for the construction of Ethernet switches, named MOTIM. The main requirement of MOTIM is to allow achieving low latency and high throughput with a generic structure that can be easily scaled. In order to make the architecture scalable, its design is based on the use of a network on chip (NoC), a concept recently proposed for enhancing SoC interconnect design [1][2]. NoCs stand as a good compromise between silicon cost and performance scalability, easing to attain design requirements. Minkenberg et al. recently identified a set of trends arising in packet switch design and discussed their consequences [3]. The most important of these trends indicates that the aggregate throughput will grow by increasing the amount of ports in switches, rather than by increasing port speed. This imposes a demand for larger crossbars, a structure that do not scale well. Scalable NoCs are a feasible alternative to implement switches with fully interconnected ports. The concept of the MOTIM switch architecture derived initially from an industry-academy cooperation targeting the implementation of the Ethernet-SDH multiplexer. In this multiplexer, the switch works with 24 bidirectional Ethernet ports working at 100Mb/s and I to 4 high-speed (I or 10Gb/s) ports. Figure I details the internal structure of the MOTIM instance used in the multiplexer. The current version contains only the Fast Ethernet ports. Gigabit ports are future work. Four module types compose the architecture: Ethernet MACs, Packet-Cell (PC) modules, Network Interfaces (NI), and the Network-on-Chip (NoC).