Technique research of event-based timing system

Background The timing system of BEPC-II is established based on event generator and event receiver (EVR) modules from the Micro-Research Finland. Though it works smoothly, there are some downsides; for example, the output pulses cannot be adjusted in picosecond accuracy in EVRs, and additional hardware modules besides EVR had to be developed to generate the revolution frequency of synchrotron radiation ring of BEPC-II. Purpose The purpose is to research the technique details of event timing system and to develop hardware modules by ourselves using FPGA, based on which further improvement in BEPC-II timing system can be made. Results The homemade hardware cards have run successfully and generated synchronous trigger pulses and clocks. The jitter is under 15 ps.