共 50 条
- [1] Dead-time compensation of 3-level NPC inverter for medium voltage IGCT drive system [J]. PESC 04: 2004 IEEE 35TH ANNUAL POWER ELECTRONICS SPECIALISTS CONFERENCE, VOLS 1-6, CONFERENCE PROCEEDINGS, 2004, : 3524 - 3528
- [2] A Compensation Method to reduce sampling delay of Zero Dead-time PWM using 3-Level NPC PWM Inverter [J]. 2016 IEEE TRANSPORTATION ELECTRIFICATION CONFERENCE AND EXPO, ASIA-PACIFIC (ITEC ASIA-PACIFIC), 2016, : 465 - 469
- [3] Zero Dead-time PWM Implementation Method for Reducing Total Harmonic Distortion in 3-Level NPC Inverter [J]. 2015 18TH INTERNATIONAL CONFERENCE ON ELECTRICAL MACHINES AND SYSTEMS (ICEMS), 2015, : 1069 - 1073
- [5] A Novel Method for Dead-Time Compensation of the Inverter Using SVPWM [J]. ADVANCES IN MULTIMEDIA, SOFTWARE ENGINEERING AND COMPUTING, VOL 2, 2011, 129 : 563 - 568
- [6] A Novel Dead-time Compensation Strategy of Three-level Inverter [J]. 2014 IEEE TRANSPORTATION ELECTRIFICATION CONFERENCE AND EXPO (ITEC) ASIA-PACIFIC 2014, 2014,
- [7] SVPWM strategy for inverter dead-time compensation [J]. Qinghua Daxue Xuebao/Journal of Tsinghua University, 2008, 48 (07): : 1077 - 1080
- [8] Dead-time Compensation Scheme for Adjustable Dead-time Controlled Resonant Snubber Inverter [J]. 2009 IEEE 6TH INTERNATIONAL POWER ELECTRONICS AND MOTION CONTROL CONFERENCE, VOLS 1-4, 2009, : 210 - 215