A Transaction Level Assertion Verification Framework in SystemC: an Application Study

被引：4

作者：

Tomasena, K. ^{[1
]}

Sevillano, J. F. ^{[1
]}

Perez, J. ^{[2
]}

Cortes, A. ^{[1
]}

Velez, I. ^{[1
]}

机构：

[1] Univ Navarra, CEIT, Manuel Lardizabal 15, San Sebastian, Spain

[2] SISTEPLANT, Parque Tecnololico Bizkaia, Derio, Spain

来源：

2009 SECOND INTERNATIONAL CONFERENCE ON ADVANCES IN CIRCUITS, ELECTRONICS AND MICRO-ELECTRONICS | 2009年

关键词：

Transaction Level Modeling; Assertion Based Verification; SystemC;

D O I：

10.1109/CENICS.2009.24

中图分类号：

TM [电工技术]; TN [电子技术、通信技术];

学科分类号：

0808 ; 0809 ;

摘要：

This paper presents a new transaction level assertion verification framework built on top of SystemC to support the integration of Assertion Based Verification in a Model Driven Design methodology. A key point of the proposed framework is that it enables decoupling the work of the design and verification teams. This is possible thanks to data introspection capabilities; the fact that the assertions are not embedded in the design model code; and the abstraction in the property specification. Thus, the two teams can work in parallel starting from the natural language specification, reducing the development time.

引用

页码：75 / +

页数：2

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