Analysis of Hardware Trojan Resilience Enabled through Logic Locking

被引:1
|
作者
Cruz, Jonathan [1 ]
Gaikwad, Pravin [1 ]
Bhunia, Swarup [1 ]
机构
[1] Univ Florida, Dept Elect & Comp Engn, Gainesville, FL 32611 USA
关键词
Hardware Trojan; Logic Locking; Metric;
D O I
10.1109/ASIANHOST56390.2022.10022237
中图分类号
TP18 [人工智能理论];
学科分类号
081104 ; 0812 ; 0835 ; 1405 ;
摘要
Emerging threats to hardware Intellectual Property (IP) confidentiality due to the horizontal business model have come in the form of piracy, reverse engineering, and extraction of design secrets. These threats have led to the development of promising IP protection solutions, which include logic locking and hardware obfuscation. While logic locking has been mainly developed for protecting confidentiality of hardware IPs, it may also provide other security benefits that extend beyond IP theft and into defending design integrity against malicious design modifications, referred to as hardware Trojan attacks. Hardware Trojan attacks are realized through insertion of stealthy malicious logic in a design, often activated under rare conditions, so as to evade detection. Existing countermeasures against Trojan attacks primarily focus on detection of an attack through targeted verification approach or its prevention through design solutions. In this paper, we present an investigation on the role of state-of-the-art logic locking methods for protecting against hardware Trojan attacks. We discuss beneficial attributes of logic locking that can contribute to Trojan prevention and significant reduction in its efficacy. We introduce metrics to describe and quantify these phenomena. Through extensive experimental validation and practical Trojan insertion, we show that on average effective logic locking can offer around 87% reduction in Trojan activation success and around 1000x increase in Trojan activation probability of those successfully inserted.
引用
收藏
页数:6
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