Design of Low Parasitic Inductance Three-level T-type SiC-MOS/Si-IGBT Module

被引：0
|
作者：
Wang, Ye [1 ]
Chen, Min [1 ]
Xu, Dehong [1 ]
机构：
[1] Zhejiang Univ, Inst Power Elect, Hangzhou, Peoples R China
来源：
2021 IEEE 12TH ENERGY CONVERSION CONGRESS AND EXPOSITION - ASIA (ECCE ASIA) | 2021年
基金：
中国国家自然科学基金;
关键词：
hybrid module; stacked substrates; parasitic inductance; inverter; HALF-BRIDGE MODULE; POWER MODULE;
D O I：
10.1109/ECCE-Asia49820.2021.9479028
中图分类号：
X [环境科学、安全科学];
学科分类号：
08 ; 0830 ;
摘要：
In this paper, a low parasitic inductance three-level T-type SiC-MOS/Si-IGBT module for distributed photovoltaic application is designed. Analysis of the current commutation loops of this hybrid module is presented. To reduce parasitic inductance, a stacked substrates structure is used to form vertical power commutation loop. A stacked bond wire substrates structure is adopted. Finally, a hybrid module with stacked bond wire substrates structure is built and testing results are provided.
引用
收藏
页码：336 / 342
页数：7
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