A scalable parallel computational core for embedded processing

Embedded computational hardware has become prevalent in recent years for communications signal processing for reasons including size and cost. The availability of competing single processor solutions from traditional vendors gives system designers a degree of choice. Some recent market entrants have even embraced parallel concepts within their architectures. However the fact remains that while one particular computational device or parallel configuration may suit a given application, it seldom suits a broad range of other applications. This promotes design inefficiency: either developers familiar with one solution from a previous project choose to use it for the next project despite some probable degree of mismatch, or they are faced with a costly learning curve implied in the adoption of a different, but possibly better matched, architecture. A preferable approach is to allow computational hardware to be adapted at a micro- and macro-architectural level to fit requirements on a project-to-project basis, but maintaining common instruction set and development tools. This gives designers the flexibility to choose the degree of parallelism and type of parallel arrangement required for their application, but without requiring a new tool and hardware learning curve. This paper describes the 2ke, a flexible and modular computational system that allows developers to standardise on one processor, instruction set, software architecture and toolchain for many projects. Architectural enhancements to its forerunner, the 2ke, are presented to permit micro-architectural parallelism to be chosen along a continuum from SISD at one extreme to full SIMD at the other, whilst the very nature of the 2ke permits extension to MIMD along an orthogonal development direction. Results in terms of logic cell usage, current consumption and memory usage will be presented for each arrangement for example application code.