Recursive Pre-Distorter for Hardware Efficient Digital Pre-Distortion

被引:2
|
作者
Byrne, Declan [1 ]
Farrell, Ronan [1 ]
Dooley, John [1 ]
机构
[1] Maynooth Univ, Maynooth, Kildare, Ireland
基金
爱尔兰科学基金会;
关键词
digital pre-distortion; polynomial evaluation; 5G; FPGA; DSP;
D O I
10.1109/PAWR51852.2021.9375537
中图分类号
TM [电工技术]; TN [电子技术、通信技术];
学科分类号
0808 ; 0809 ;
摘要
In this paper, a novel recursive pre-distorter design to minimize the hardware requirements for digital pre-distortion is proposed. The proposed structure is modular and can be adapted easily to implement subset, reduced or regularised digital pre-distortion functions. For MIMO systems, in which each transmission element requires linearisation and each pre-distortion function can differ, the hardware efficiency and flexibility provided by the proposed pre-distorter is hugely beneficial. Compared to Horner's method the novel method enables a 62% reduction in the hardware resources required to implement a 5th order, 2 memory tap Volterra pre-distortion function.
引用
收藏
页码:31 / 33
页数:3
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