28nm Node Process Optimization: A Lithography Centric View

被引:1
|
作者
Seltmann, Rolf [1 ]
机构
[1] Module One LLC & Co KG, GLOBALFOUNDRIES Dresden, D-01109 Dresden, Germany
来源
30TH EUROPEAN MASK AND LITHOGRAPHY CONFERENCE | 2014年 / 9231卷
关键词
28nm node; yield; scanner; SMO; planarity; focus; process window;
D O I
10.1117/12.2068020
中图分类号
O43 [光学];
学科分类号
070207 ; 0803 ;
摘要
Many experts claim that the 28nm technology node will be the most cost effective technology node forever. This results from primarily from the cost of manufacturing due to the fact that 28nm is the last true Single Patterning (SP) node. It is also affected by the dramatic increase of design costs and the limited shrink factor of the next following nodes. Thus, it is assumed that this technology still will be alive still for many years. To be cost competitive, high yields are mandatory. Meanwhile, leading edge foundries have optimized the yield of the 28nm node to such a level that that it is nearly exclusively defined by random defectivity. However, it was a long way to go to come to that level. In my talk I will concentrate on the contribution of lithography to this yield learning curve. I will choose a critical metal patterning application. I will show what was needed to optimize the process window to a level beyond the usual OPC model work that was common on previous nodes. Reducing the process (in particular focus) variability is a complementary need. It will be shown which improvements were needed in tooling, process control and design-mask-wafer interaction to remove all systematic yield detractors. Over the last couple of years new scanner platforms were introduced that were targeted for both better productivity and better parametric performance. But this was not a clear run-path. It needed some extra affords of the tool suppliers together with the Fab to bring the tool variability down to the necessary level. Another important topic to reduce variability is the interaction of wafer none-planarity and lithography optimization. Having an accurate knowledge of within die topography is essential for optimum patterning. By completing both the variability reduction work and the process window enhancement work we were able to transfer the original marginal process budget to a robust positive budget and thus ensuring high yield and low costs.
引用
收藏
页数:10
相关论文
共 50 条
  • [1] Research of SMO process to improve the imaging capability of lithography system for 28nm node and beyond
    Yu, Haibin
    Zhang, Yueyu
    Jiang, Binjie
    Yu, Shirui
    Mao, Zhibiao
    2017 CHINA SEMICONDUCTOR TECHNOLOGY INTERNATIONAL CONFERENCE (CSTIC 2017), 2017,
  • [2] Joint-Optimization for SRAM and Logic for 28nm node and below
    Verhaegen, Staf
    Smayling, Michael C.
    De Bisschop, Peter
    Laenens, Bart
    DESIGN FOR MANUFACTURABILITY THROUGH DESIGN-PROCESS INTEGRATION IV, 2010, 7641
  • [3] A STUDY OF AA CD UNIFORMITY LOADING OPTIMIZATION AT 28NM NODE
    Zhu, YiZheng
    Lu, Lian
    Chen, Fuhong
    Chan, Sifei
    Li, Quanbo
    Zhang, Yu
    Pang, Albert
    2017 CHINA SEMICONDUCTOR TECHNOLOGY INTERNATIONAL CONFERENCE (CSTIC 2017), 2017,
  • [4] The Study of 28nm Node Poly Double Patterning Integrated Process
    Li, Zhonghua
    Li, Runling
    Guan, Tianpeng
    Liu, Biqiu
    Mao, Xiaoming
    Meng, Xiangguo
    Li, Quanbo
    Li, Fang
    Yang, Zhengkai
    Zhang, Yu
    Pang, Albert
    2015 China Semiconductor Technology International Conference, 2015,
  • [5] NICKEL SILICIDE ANNEAL PROCESS RESEARCH FOR 28NM CMOS NODE
    Wen, Zhenping
    Cheng, Xinhua
    Fang, Jingxun
    2017 CHINA SEMICONDUCTOR TECHNOLOGY INTERNATIONAL CONFERENCE (CSTIC 2017), 2017,
  • [6] Power Optimization Approach of ORCA Processor for 32/28nm Technology Node
    Babayan, Davit
    TENTH INTERNATIONAL CONFERENCE ON COMPUTER SCIENCE AND INFORMATION TECHNOLOGIES REVISED SELECTED PAPERS CSIT-2015, 2015, : 11 - 14
  • [7] OPTIMIZATION OF 28NM HK/MG SINGLE WAFER CLEANING PROCESS
    Liang, Haihui
    Liu, JiaLei
    Liu, HuanXin
    He, Yonggen
    Wu, Jingang
    Ge, Xiaojing
    Haigermoser, Christian
    2016 CHINA SEMICONDUCTOR TECHNOLOGY INTERNATIONAL CONFERENCE (CSTIC), 2016,
  • [8] CPI Challenges to BEOL at 28nm Node and Beyond
    Ryan, Vivian
    Breuer, Dirk
    Geisler, Holm
    Kioussis, Dimitri
    Lehr, Matthias U.
    Paul, Jens
    Machani, Kashi
    Shah, Chirag
    Kosgalwies, Sven
    Lehmann, Lothar
    Lee, Jaesik
    Kuechenmeister, Frank
    Ryan, E. Todd
    Karimanal, Kamal
    2012 IEEE INTERNATIONAL RELIABILITY PHYSICS SYMPOSIUM (IRPS), 2012,
  • [9] Fabrication of 28nm pitch Si fins with DSA lithography
    Schmid, Gerard
    Farrell, Richard
    Xu, Ji
    Park, Chanro
    Preil, Moshe
    Chakrapani, Vidhya
    Mohanty, Nihar
    Ko, Akiteru
    Cicoria, Michael
    Hetzer, David
    Somervell, Mark
    Rathsack, Benjamen
    ALTERNATIVE LITHOGRAPHIC TECHNOLOGIES V, 2013, 8680
  • [10] Thin Film Challenges in 28nm Technology Node
    Zhang, Beichao
    Zhang, Bin
    Xiao, Haibo
    Deng, Hao
    Tong, Hao
    Tan, Jingjing
    Zhou, Ming
    Li, Nicola
    Guo, Shibi
    Ren, Wanchun
    Wang, Xiaona
    Jing, Xuezheng
    Xiang, Yanghui
    Ping, Yanlei
    Bao, Yu
    Zhang, Ziying
    Wang, Zengtao
    Lu, Wei
    Wu, Jinggang
    CHINA SEMICONDUCTOR TECHNOLOGY INTERNATIONAL CONFERENCE 2012 (CSTIC 2012), 2012, 44 (01): : 391 - 394