Real-time FPGA Implementation of Lu's Chaotic Generator for Cipher Embedded Systems

In this paper, a new approach to real-time FPGA implementation of chaotic generator of the random key based Lu's chaotic generator for data stream encryption is presented. We propose a structural hardware architecture designed for a small chip area and high speed performance. This architecture is particularly attractive since it provides a low-cost security telecommunication solution while holding or increasing the encryption throughput rate. We show its feasibility through implementation which is detailed and discussed using Virtex Xilinx FPGA. This architecture employs only 1115 slices and allows achieving a random key throughput rate of 182.9 Mbps by using a low system clock with a frequency of up to 22.868 MHz allowing low power consumption especially for embedded applications.