Analysis of Linear Interface Algorithms for Power Hardware-in-the-Loop Simulation

Power hardware-in-the-loop (PHIL) simulation is a technique whereby actual power hardware is interfaced to a virtual surrounding system, simulated in real-time, through PHIL interfaces making use of power amplifiers and/or actuators. A number of seemingly disparate interface algorithms (IA) have been proposed in the literature for achieving the virtual coupling between the simulated and physical portions of the system, with each presenting different strengths and shortcomings. In this work, a framework based on an architecture for bilateral teleoperation systems is described, which is suitable for the formulation of linear PHIL IAs, encompassing the majority of the existing IAs proposed in the literature. Formulations of a number of existing PHIL IAs are given in the context of the described framework. Requirements for achieving transparency with the IAs are described, and several of the existing IAs are discussed in terms of the framework, adherence to the transparency requirements, and performance. As the architecture also lends itself to the development of flexible IA modules for real-time simulators, the implementation and application of an IA module reflecting this architecture is also described.