Advances in hardware architectures for image and video coding - A survey

被引：36

作者：

Tseng, PC ^{[1
]}

Chang, YC ^{[1
]}

Huang, YW ^{[1
]}

Fang, HC ^{[1
]}

Huang, CT ^{[1
]}

Chen, LG ^{[1
]}

机构：

[1] Natl Taiwan Univ, DSP IC Design Lab, Grad Inst Elect Engn, Dept Elect Engn, Taipei 106, Taiwan

来源：

PROCEEDINGS OF THE IEEE | 2005年 / 93卷 / 01期

关键词：

hardware architecture; H.264/AVC; image coding; JPEG; 2000; MPEG-4; very large scale integration (VLSI); video coding;

D O I：

10.1109/JPROC.2004.839622

中图分类号：

TM [电工技术]; TN [电子技术、通信技术];

学科分类号：

0808 ; 0809 ;

摘要：

This paper provides a survey of state-of-the-art hardware architectures for image and video coding. Fundamental design issues are discussed with particular emphasis on efficient dedicated implementation. Hardware architectures for MPEG-4 video coding and JPEG 2000 still image coding are reviewed as design examples, and special approaches exploited to improve efficiency are identified. Further perspectives are also presented to address the challenges of hardware architecture design for advanced image and video-coding in the future.

引用

页码：184 / 197

页数：14

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