A 0.6-1V Input Capacitor-Less Asynchronous Digital LDO with Fast Transient Response Achieving 9.5b over 500mA Loading Range in 65-nm CMOS

被引：0

作者：

Yang, Fan ^{[1
]}

Mok, Philip K. T. ^{[1
]}

机构：

[1] Hong Kong Univ Sci & Technol, Dept Elect & Comp Engn, Hong Kong, Hong Kong, Peoples R China

来源：

ESSCIRC CONFERENCE 2015 - 41ST EUROPEAN SOLID-STATE CIRCUITS CONFERENCE (ESSCIRC) | 2015年

关键词：

POWER MANAGEMENT; REGULATOR; SOC;

D O I：

暂无

中图分类号：

TM [电工技术]; TN [电子技术、通信技术];

学科分类号：

0808 ; 0809 ;

摘要：

A 65-nm external capacitor-less asynchronous digital low drop-out regulator (DLDO) with adaptive sizing and fast transient response is presented in this paper. Operating at a wide input voltage range from as low as 0.6V to 1V, this DLDO is capable of delivering a maximum current of 500mA with 50mV drop-out voltage. The proposed adaptive sizing featured by row-column-bit 3-dimensional (3D) power stage and its asynchronous adaptive digital pipeline control have enabled a fast transient response to nanoseconds' loading current change and a 200mV per 10ns reference voltage switching, as well as a fine resolution of 768 levels (similar to 9.5 bits) with a 5mV output ripple. The quiescent current consumed by this DLDO at steady operation is as low as 300 mu A over the whole input range.

引用

页码：180 / 183

页数：4