Analysis of Subthreshold Swing and Internal Voltage Amplification for Hysteresis-Free Negative Capacitance FinFETs

We present the device design guideline for hysteresis-free negative capacitance FinFETs (NC-FinFETs) to enhance the internal voltage amplification (A(V)) and reduce the subthreshold swing (SS) (E-c). can be increased by increasing fin width (Wfin), coercive field (Ec), and thickness of the ferroelectric layer (TFE), and A(V) can also be enhanced by reducing EOT, channel length (L-ch), buried oxide thickness (Tbox), fin height (Hfin) and remnant polarization (P0). The subthreshold swing improvements of NC-FinFETs over FinFETs become larger as A(V) increases. With the same channel length, compared with the NC-FinFET without underlap design, NC-FinFET with underlap design exhibits better capacitance matching and larger Lch, hence showing larger subthreshold swing improvement and oncurrent improvement over FinFET. At shorter L-ch (= 12.5nm), NC-FinFETs with underlap design exhibit 73.6% improvements in intrinsic delay compared with the FinFETs due to its larger effective drive current.