A design of an associative memory array processor for ultrasonograph image acquisition and processing

被引:0
|
作者
Aly, GM [1 ]
El-Nadi, NM [1 ]
Fayed, ZT [1 ]
Faheem, HM [1 ]
机构
[1] Ain Shams Univ, Fac Engn, Dept Comp & Control Syst, Cairo, Egypt
关键词
associative memory array processor; ultrasonograph image processing;
D O I
暂无
中图分类号
R318 [生物医学工程];
学科分类号
0831 ;
摘要
This paper describes a design of an associative memory array processor that can be used in the acquisition and processing of ultrasonograph images. The major concept is to design a parallel architecture that reduces task's execution time by analyzing multiple parts of the image concurrently. The architecture constitutes a distinctive type of single-instruction stream, multiple-data stream machine that is built around content-addressable associative memory slabs, that allow parallel access of multiple memory words. The basic building block of this architecture is a one-pixel processing element, which can perform the standard load (data acquisition) function and also contains some special comparison logic to enable its content to be compared with an external data. Several image processing operations are implemented in parallel, among them: component labeling, size filtering, pattern centralization, and pattern recognition. The proposed novel architecture can label specific regions into the image and isolate them intelligently. It is also capable of storing templates that may be considered as references for similar cases. The system is able to perform learning process and extract features from several input patterns and store the reference pattern in a slice. Moreover, the system is capable of comparing an input image with a pre-stored template during recognition process. The proposed architecture is of interest because it speeds up the recognition process and helps radiology specialists to write their reports confidently.
引用
收藏
页码:283 / 288
页数:6
相关论文
共 50 条
  • [1] AN ASSOCIATIVE PROCESSOR ARRAY FOR IMAGE-PROCESSING
    DULLER, AWG
    STORER, RH
    THOMSON, AR
    DAGLESS, EL
    IMAGE AND VISION COMPUTING, 1989, 7 (02) : 151 - 158
  • [2] DESIGN OF AN ASSOCIATIVE PROCESSOR ARRAY
    DULLER, AWG
    STORER, RH
    THOMSON, AR
    DAGLESS, EL
    POUT, MR
    MARRIOT, AP
    GOLDFINCH, J
    IEE PROCEEDINGS-E COMPUTERS AND DIGITAL TECHNIQUES, 1989, 136 (05): : 374 - 382
  • [3] DESIGN OF AN ARRAY PROCESSOR FOR IMAGE-PROCESSING
    LEE, D
    JOURNAL OF PARALLEL AND DISTRIBUTED COMPUTING, 1991, 11 (02) : 163 - 169
  • [4] IMAGE-PROCESSING WITH AN ARRAY PROCESSOR
    RANZINGER, H
    PROCEEDINGS OF THE SOCIETY OF PHOTO-OPTICAL INSTRUMENTATION ENGINEERS, 1983, 397 : 392 - 397
  • [5] Design optimization of VLSI array processor architecture for window image processing
    Li, DJ
    Jiang, L
    Kunieda, H
    IEICE TRANSACTIONS ON FUNDAMENTALS OF ELECTRONICS COMMUNICATIONS AND COMPUTER SCIENCES, 1999, E82A (08) : 1475 - 1484
  • [6] Design optimization of VLSI array processor architecture for window image processing
    Tokyo Inst of Technology, Tokyo, Japan
    IEICE Trans Fund Electron Commun Comput Sci, 8 (1475-1484):
  • [7] COMPILING A VECTOR AND ARRAY-PROCESSING LANGUAGE FOR AN ASSOCIATIVE PROCESSOR
    BREZANY, P
    SIPKOVA, V
    MICROPROCESSING AND MICROPROGRAMMING, 1992, 34 (1-5): : 171 - 174
  • [8] High performance processor array for image processing
    Foldesy, Peter
    Zarandy, Akos
    Rekeczky, Csaba
    Roska, Tamas
    2007 IEEE INTERNATIONAL SYMPOSIUM ON CIRCUITS AND SYSTEMS, VOLS 1-11, 2007, : 1177 - 1180
  • [9] Associative Memory Design for the FastTrack Processor (FTK) at ATLAS
    Annovi, A.
    Beccherle, R.
    Beretta, M.
    Bossini, E.
    Crescioli, F.
    Dell'Orso, M.
    Giannetti, P.
    Hoff, J.
    Liu, T.
    Liberali, Y.
    Sacco, I.
    Schoening, A.
    Soltveit, H. K.
    Stabile, A.
    Tripiccione, R.
    Volpi, G.
    2011 IEEE NUCLEAR SCIENCE SYMPOSIUM AND MEDICAL IMAGING CONFERENCE (NSS/MIC), 2011, : 141 - 146
  • [10] Programmable design for memory sharing processor array
    Li, DJ
    Kunieda, H
    ISCAS '97 - PROCEEDINGS OF 1997 IEEE INTERNATIONAL SYMPOSIUM ON CIRCUITS AND SYSTEMS, VOLS I - IV: CIRCUITS AND SYSTEMS IN THE INFORMATION AGE, 1997, : 2048 - 2051