An Integrated CMOS Front-End Receiver with a Frequency Tripler for V-Band Applications

A direct-conversion receiver integrated with the CMOS subharmonic frequency tripler (SET) for V-band applications is designed, fabricated and measured using 0.13-mu m CMOS technology. The receiver consists of a low-noise amplifier, a down-conversion mixer, an output buffer, and an SET. A fully differential SFT is introduced to relax the requirements on the design of the frequency synthesizer. Thus, the operational frequency of the frequency synthesizer in the proposed receiver is only 20 GHz. The fabricated receiver has a maximum conversion gain of 19.4 dB, a minimum single-side band noise figure of 10.2 dB, the input-referred 1-dB compression point of -20 dBm and the input third order inter-modulation intercept point of -8.3 dB. It draws only 15.8 mA from a 1.2-V power supply with a total chip area of 0.794 mm x 0.794 mm. As a result, it is feasible to apply the proposed receiver in low-power wireless transceiver in the V-band applications.