Multi-Threaded control of NAND Flash memory array

被引:2
|
作者
Nubile, Luca [1 ]
De Santis, Luca [1 ]
Cardinali, Riccardo [1 ]
机构
[1] Micron Semicond Italy, Avezzano, Italy
关键词
Flash memories; Integrated Circuit design; Multitasking; Parallel algorithms; Multi-Threading;
D O I
10.1109/WMED49473.2021.9425137
中图分类号
TM [电工技术]; TN [电子技术、通信技术];
学科分类号
0808 ; 0809 ;
摘要
Flash memory devices operations like read, program and erase are performed by sequences called "algorithms". An algorithm is mainly composed of phases where accurate voltages are computed and applied to the array cells and phases where data are moved through different latches in data buffers. The fast-increasing complexity of multi-bit NAND memory algorithms made it natural to realize control logic on a microprocessor, in the form of firmware routines. The HW/FW co-design enables a safer complexity management, allows development of algorithms in parallel with physical design and allows acceleration of development time to fit aggressive time-to-market requirements. Again, to follow the increasingly performance requirements different kind of multi-thread microprocessor solutions have been proposed in the years to get the best performance-power-area (PPA) trade-off. This article proposes one possible approach to performance optimization by a multi-threaded approach, without an immediate downside for area and power. The most innovative point of the new architecture is the deep adherence between intrinsic paralleliz able physical processes inside a NAND Flash and the number of threads, busses and physical executors. As shown, this solution introduces tangible advantages in terms of performance.
引用
收藏
页码:28 / 31
页数:4
相关论文
共 50 条
  • [1] A new concurrency control mechanism for multi-threaded environment using transactional memory
    Ghosh, Ammlan
    Chaki, Rituparna
    Chaki, Nabendu
    [J]. JOURNAL OF SUPERCOMPUTING, 2015, 71 (11): : 4095 - 4115
  • [2] A new concurrency control mechanism for multi-threaded environment using transactional memory
    Ammlan Ghosh
    Rituparna Chaki
    Nabendu Chaki
    [J]. The Journal of Supercomputing, 2015, 71 : 4095 - 4115
  • [3] Adaptive control in multi-threaded iterated integration
    de Doncker, Elise
    Yuasa, Fukuko
    [J]. IC-MSQUARE 2012: INTERNATIONAL CONFERENCE ON MATHEMATICAL MODELLING IN PHYSICAL SCIENCES, 2013, 410
  • [4] An efficient multi-threaded memory allocator for PDES applications
    Li, Tianlin
    Yao, Yiping
    Tang, Wenjie
    Zhu, Feng
    Lin, Zhongwei
    [J]. SIMULATION MODELLING PRACTICE AND THEORY, 2020, 100
  • [5] Memory management for multi-threaded software DSM systems
    Kee, YS
    Kim, JS
    Ha, S
    [J]. PARALLEL COMPUTING, 2004, 30 (01) : 121 - 138
  • [6] NAND flash memory controller for image flash array in space
    [J]. Li, J. (664910696@99.com), 2012, Board of Optronics Lasers, No. 47 Yang-Liu-Qing Ying-Jian Road, Tian-Jin City, 300380, China (23):
  • [7] Progress in cancellable, multi-threaded, control software
    Shortridge, K.
    Farrell, T. J.
    [J]. SOFTWARE AND CYBERINFRASTRUCTURE FOR ASTRONOMY, 2010, 7740
  • [8] A multi-threaded simulator for a distributed control system
    Jones, IR
    Tracy, DP
    [J]. 2003 IEEE INTERNATIONAL CONFERENCE ON SYSTEMS, MAN AND CYBERNETICS, VOLS 1-5, CONFERENCE PROCEEDINGS, 2003, : 2272 - 2277
  • [9] Multi-threaded reachability
    Sahoo, D
    Jain, J
    Iyer, SK
    Dill, DL
    Emerson, EA
    [J]. 42ND DESIGN AUTOMATION CONFERENCE, PROCEEDINGS 2005, 2005, : 467 - 470
  • [10] SAC - A functional array language for efficient multi-threaded execution
    Grelck, Clemens
    Scholz, Sven-Bodo
    [J]. INTERNATIONAL JOURNAL OF PARALLEL PROGRAMMING, 2006, 34 (04) : 383 - 427